1. Field of the Invention
The invention relates generally to semiconductor device having at least two field effect transistors, and more particularly, to a complementary field effect transistor improved so as to have both reliability and high speed in an N channel MOSFET and without punch-through in a P channel MOSFET. This invention relates to a method of manufacturing such a complementary field effect transistor.
2. Description of the Background Art
At present, complementary field effect transistors (referred to as CMOSFET hereinafter) are employed in very large scale LSIs, for example in dynamic random access memories, because of its characteristics of low power consumption and easy circuit design. The N channel MOSFET and the P channel MOSFET used in CMOS circuits have surface channel structures and buried channel structures, respectively, as the result of being formed by simplified manufacturing processing, as shown in FIGS. 4A and 4B.
Surface channel structures and buried channel structures will be explained in detail in reference to the figures. FIG. 4A is a sectional view of a conventional CMOSFET. FIG. 4B is a channel profile of a NMOS, whereas FIG. 4C is a channel profile of a PMOS. Referring to these figures, a P well 2 and an N well 3 are formed on a P type semiconductor substrate 1. An N channel MOSFET 5 is formed in P well 2, while a P channel MOSFET 6 is formed in N well 3. Each of the gate electrodes 4a, 4b is made the N type. Because gate electrodes 4a, 4b are of the N type, the channel region 7 of N channel MOSFET 5 becomes P type, and N channel MOSFET 5 is of the surface channel structure. On the other hand, the channel region 8 of P channel MOSFET 6 becomes P type, and P channel MOSFET 6 is of the buried channel structure.
As the device becomes more minute, the gate length of N channel MOSFET 5 and P channel MOSFET 6 becomes shorter. This gives rise to the problem that reliability is deteriorated due to hot carriers of N channel MOSFET 5. In other words, if the channel length becomes shorter, the electric field near the drain becomes very high under a constant supply voltage. This causes some of the hot electrons obtaining high energy from the electric field to be implanted into the gate oxide film, wherein they remain to change the threshold voltage of the transistor little by little. This is the problem caused by hot carriers.
An N channel MOSFET having a lightly doped drain structure (LDD) has been devised to solve the above mentioned problem caused by hot electrons for improving the reliability of the N channel MOSFET.
FIG. 1B is a sectional view of a conventional CMOSFET comprising an N channel MOSFET having a LDD structure. FIGS. 5A-5F are sectional views of the manufacturing steps of the CMOSFET shown in FIG. 1B. Referring to these figures, a method of manufacturing a conventional CMOSFET comprising an N channel MOSFET having an LDD structure will be described.
Referring to FIG. 5A, a P well 2 and an N well 3 are formed on semiconductor substrate 1. A gate oxide film 8a is formed on the surface of P well 2. Gate electrode 4a comprising N type impurities is formed on gate oxide film 8a. Similarly, a gate oxide film 8b is formed on the surface of N well 3, and gate electrode 4b comprising N type impurities is formed on gate oxide film 8b. Gate oxide films 8a and 8b are formed at the same time. Also, gate electrodes 4a and 4b are formed at the same time. The purpose of implanting N type impurities into gate electrode 4a, 4b is to raise the conductivity of the gate electrode.
Referring to FIG. 5B, the N well 3 side is covered by a resist 9. Using gate electrode 4a as the mask, N type impurity ions of relatively low concentration are implanted into the main surface of P well 2. As a result, N type impurity region 10 of relatively low concentration is formed in the main surface of P well 2 at both sides of gate electrode 4a. Then, resist 9 is removed.
Referring to FIG. 5C, an oxide film 11 is deposited over semiconductor substrate 1 so as to cover gate electrodes 4a and 4b.
Referring to FIGS. 5C and 5D, oxide film 11 is etched back by anisotropic etching to form sidewall spacers 12 on the sidewalls of gate electrodes 4a, 4b.
Referring to FIG. 5E, the N well 3 side is covered by resist 9. N type impurity ions of relatively high concentration are implanted into the main surface of P well 2. As a result, an impurity region 13 having a concentration higher than that of impurity region 10 is formed which joins impurity region 10 of low concentration in the main surface of P well 2. The concentration of impurity region 10 is generally set to be approximately 1/100 of the concentration of impurity region 13 to form LDD structure. Next, resist 9 is removed.
Referring to FIG. 5F, the P well 2 side is covered by resist 9. Using gate electrode 4b and sidewall spacers 12 as the mask, P type impurity ions are implanted into the main surface of N well 3. As a result, a P type impurity region 14 is formed in the main surface of N well 3 at both sides of gate electrode 4b. Because the diffusion rate of P type impurities is high, the impurities diffuse as far as to the edge of gate electrode 4b. In the above described manner, a CMOSFET comprising an N channel MOSFET of the LDD structure shown in FIG. 1B is formed.
The problems of the CMOSFET comprising an N channel MOSFET of the LDD structure shown in FIG. 1B will be explained hereinafter.
Referring to FIG. 1B, the width of sidewall spacer 12 is L.sub.SW, while the width of impurity region 10 of low concentration is L.sub.n -. L.sub.n - must be not less than 0.2 .mu.m to reduce the electric field in the vicinity of the drain which generates hot carriers. However, impurity region 10 of low concentration cannot easily extend beneath gate electrode 4a because it is formed by implanting ions perpendicularly, as shown in FIG. 5B. In order to obtain L.sub.n - of not less than 0.2 .mu.m, impurity region 13 of high concentration must be formed at a position far away from gate electrode 4a. Accordingly, it is necessary to have a considerably wide L.sub.SW. A typical value of L.sub.SW is 0.3 .mu.m.
Such an LDDMOSFET has the following two serious problems. The first problem is that impurity region 10 of low concentration located below sidewall spacer 12 changes to substantially high concentration by the gate electric field only in the region as far as to approximately 0.05 .mu.m from the edge of gate electrode 4a. The major part of impurity region 10 of low concentration beneath sidewall spacer 12 remains as a high resistance layer even at the time of applying gate voltage. As a result, current handling capability and high speed are decreased.
The second problem is that hot electrons generated by the electric field are implanted into sidewall spacer 12, due to the fact that the maximum point of the electric field in the drain exists beneath sidewall spacer 12, as shown in FIG. 2B(2). This causes the low concentration of impurity region 10 to become increasingly lower. As a result, impurity region 10 becomes a layer of further high resistance. Referring to FIG. 6, the portion denoted with reference number 100 is the region where concentration is lowered. The current handling capability is degraded, whereby the high speed is lowered. In the right graph of FIG. 2B(2) the abscissa x represents the distance from the edge of gate electrode 4a, while the ordinate E.sub.ch represents the strength of the electric field along the direction of channel length. The same can be said in FIGS. 2A(2) and 2C(2).
LDDMOSFET comprises the above described problems. A Gate/N.sup.- overlapped LDDMOSFET has been proposed to solve these problems.
Referring to FIG. 1C, the feature of Gate/N.sup.- overlapped LDDMOSFET lies in the point that impurity region 10 of low concentration extends widely beneath gate electrode 4a. It is obvious that the problem of the LDDMOSFET shown in FIG. 1B arises from the fact that impurity region 10 of low concentration exists beneath sidewall spacer 12.
FIGS. 7A-7F are sectional views of the manufacturing steps of a CMOSFET comprising Gate/N.sup.- overlapped LDDMOSFET shown in FIG. 1C. The method of manufacturing this CMOSFET is described hereinafter.
Referring to FIG. 7A, P well 2 and N well 3 are formed on semiconductor substrate 1 Gate oxide film 8a is formed on the surface of P well 2. Gate electrode 4a comprising N type impurities is formed on gate oxide film 8a. Similarly, gate oxide film 8b is formed on the surface of N well 3, and gate electrode 4b comprising N type impurities is formed on gate oxide film 8b. Gate oxide films 8a and 8b are formed a the same time. Also, gate electrodes 4a and 4b are formed at the same time.
Referring to FIG. 7B, the N well 3 side is covered by resist 9. Next, using gate electrode 4a as a mask, N type impurity ions of relatively low concentration are implanted into the main surface of P well 2 from a direction oblique to the main surface. Impurity region 10 of relatively low concentration is formed extending below gate electrode 4a in the main surface of P well 2 at both sides of gate electrode 4a. Then, resist 9 is removed.
Referring to FIG. 7C, oxide film 11 is deposited over semiconductor substrate 1 so as to cover gate electrodes 4a and 4b.
Referring to FIGS. 7C and 7D, oxide film 11 is etched back by anisotropic etching to form sidewall spacers 12 at the sidewalls of gate electrodes 4a, 4b. The thickness of oxide film 11 is adjusted so that the width of sidewall spacer 12 becomes 0.15 .mu.m.
Referring to FIG. 7E, the N well 3 side is covered by resist 9. By implanting N type impurity ions of relatively high concentration into the main surface of P well 2, impurity region 13 having a concentration higher than that of impurity region 10 is formed in the main surface of P well 2 which joins impurity region 10. The concentration of impurity region 10 is set to be a concentration of 1/100 of the concentration of impurity region 13.
Referring to FIG. 7F, the P well 2 side is covered by resist 9. Using sidewall spacers 12 formed on the sidewalls of gate electrodes 4a and 4b, P type impurity ions are implanted into the main surface of N well 3. As a result, P type impurity region 14 is formed in the main surface of N well 3 at both sides of gate electrode 4b. Then, resist 9 is removed.
In Gate/N.sup.- overlapped LDDMOSFET formed in the above manner, the maximum point of the electric field in the drain comes below gate electrode 4a, as shown in FIG. 2C(2). Accordingly, hot electrons are not implanted into sidewall spacer 12, even if hot electrons are generated. Therefore, the state shown in FIG. 6 is avoided, where impurity region 10 of low concentration turns to a high resistance layer in the region at a distance from gate electrode 4a. As a result, decrease in high speed and deterioration of reliability do not occur. However, as shown in FIG. 7F, P.sup.+ impurity region 14 expands deeply below gate electrode 4b because the width of sidewall spacer 12 along the direction identical to the direction of the channel length is small, when P.sup.+ impurity region is formed by implanting P type impurity ions into the main surface of N well 3. This results in the generation of punch-through in the buried channel P channel MOSFET, in reference to FIG. 8.